1. Field of the Invention
The present invention relates generally to a so-called Bi-CMOS circuit in which a bipolar transistor and a CMOS transistor are combined and, more particularly, to a Bi-CMOS circuit suitable for use with a semiconductor memory device operating at a low voltage with a high speed.
2. Description of the Background Art
A Bi-CMOS circuit where bipolar circuits and CMOS circuits are combined is often employed for the purpose of speeding-up in a semiconductor memory device.
FIG. 14 is a circuit diagram of one example of the Bi-CMOS circuit, which illustrates a configuration wherein two Bi-CMOS inverter circuits 10, 11 are connected in series. NPN type bipolar transistors Q11, Q12 of a first-stage inverter and NPN type bipolar transistors Q13, Q14 of a second-stage inverter are respectively connected in series. The Bi-CMOS inverter circuits 10, 11 include a CMOS inverter I10 for controlling a base of the bipolar transistor Q11 and a CMOS inverter I11 for controlling a base of the bipolar transistor Q13. Further, N-channel MOS (NMOS) transistors M10, N10 are connected in series between the ground and a connecting point between an emitter of the bipolar transistor Q11 and a collector of the bipolar transistor Q12. Similarly, transistors M11, N11 are connected in series between the ground and a connecting point between an emitter of the bipolar transistor Q13 and a collector of the bipolar transistor Q14. A gate of the NMOS transistor M10 is connected to an input point a11 which is common to the inverter I10. A gate of the NMOS transistor M11 is connected to an input point a14 common to the inverter I11. A gate of the NMOS transistor N10 is connected to an output point a12 of the inverter I10. A gate of the NMOS transistor N11 is connected to an output point a15 of the inverter I11. Further, a connecting point between the NMOS transistors M10 and N10 is connected to a base of the bipolar transistor Q12. A connecting point between the NMOS transistors M11 and N11 is connected to a base of the bipolar transistor Q14.
Next, the operation of this circuit will be explained.
When a voltage of an [H] level is applied to the input point a11 of the CMOS inverter I10, which serves as an input point of the Bi-CMOS inverter circuit 10, a voltage of an [L] level is outputted to the output point a14. The following is the reason for this. When the input point a11 is at the [H] level, both the bipolar transistor Q11 and the NMOS transistor N10 are switched off, whereas the NMOS transistor M10 is switched ON. Hence, when a base a13 of the bipolar transistor Q12 is charged with a voltage up to Vbi, the bipolar transistor Q12 is switched ON, and discharging takes place from the output point a14, resulting in a drop of its electric potential. At this time, however, the voltage at the output point a14 goes not to Vss but Vbi because of being discharged through the bipolar transistor Q12.
On the side of the Bi-CMOS inverter circuit 11, when the voltage of the [L] level is applied to the input point a14, the NMOS transistor M11 is switched OFF, the output point a15 of the CMOS inverter I11 becomes a Vcc level, and the NMOS transistor N11 is switched ON. The bipolar transistor Q14 is thereby switched OFF. The base of the bipolar transistor Q13 is charged with the voltage up to Vbi, and the bipolar transistor Q13 is thereby switched ON, with the result that an output point a16 is charged. At this time, an electric potential at the output point a16 is charged through the bipolar transistor Q13 and therefore becomes (Vcc-Vbi) lower by Vbi than Vcc.
FIG. 13A shows potential variations at the output terminal a14 when inputting an [L] level voltage after inputting an [H] level voltage to the input terminal of the BiCMOS inverter circuit 10 of FIG. 14. As stated above, the output voltage changes from Vbi to (Vcc-Vbi) but does not change from Vss to Vcc as in the case of the output of the CMOS inverter circuit.
Thus, the output of the conventional BiCMOS circuit does not exhibit a full swing but merely changes from Vbi to (Vcc-Vbi).
Furthermore, in the Bi-CMOS inverter circuit 10 illustrated in FIG. 14, when inputting the [L] level voltage to the input point a11, the condition necessary for effecting the discharging from the output a16 in the BiCMOS inverter circuit 11 is that the NMOS transistor M11 is switched ON, and the base of the bipolar transistor Q14 is charged with the voltage up to Vbi. Additionally, at this time, the NMOS transistor N11 and the bipolar transistor Q13 are kept OFF. Herein, the NMOS transistor M11 is switched ON, and, for this purpose, it is required that a difference between a gate voltage (Vcc-Vbi) and a source voltage (Vbi) be larger than the threshold value VTHN of the NMOS transistor M11. This is expressed by the following formula: EQU Vcc.gtoreq.2Vbi+VTHN
However, with a decreasing tendency of the power supply voltage in recent years, it is difficult to ensure this relationship. Hence, it is also difficult to restrain a deterioration in terms of the delay time in the conventional Bi-CMOS inverter circuit, and a normal circuit operation cannot be secured.
Moreover, a source potential of the NMOS transistor M11 comes to Vbi owing to the bipolar transistor Q14, and, therefore, a problem arises, wherein the threshold value VTHN of the NMOS transistor M11 is larger due to a back gate effect than when the source potential is Vss.
Thus, with miniaturized transistors, decreasing the power supply voltage is desired in terms of a problem pertaining to a reliability on a MOS hot carrier and a gate oxide film. While on the other hand, it is impossible to prevent the deterioration in terms of the delay time due to the reduced voltage in the conventional Bi-CMOS inverter circuit.